{
  "me": "Sharoon Sharif",
  "areas": { "hardware": "Hardware", "ml": "Machine learning", "robotics": "Robotics" },
  "groups": [
    { "heading": "Under review", "statuses": ["Under review", "Submitted"] },
    { "heading": "In preparation", "statuses": ["In preparation"] },
    { "heading": "Published", "statuses": ["Published"] },
    { "heading": "Thesis", "types": ["thesis"] }
  ],
  "publications": [
    {
      "id": "survival-input-audit",
      "title": "Auditing Input Use in Histology–Transcriptomics Survival Models, with a One-Checkpoint Recipe for Missing Inputs",
      "authors": ["Sharoon Sharif", "H. Can"],
      "author_note": null,
      "venue": "Interdisciplinary Sciences: Computational Life Sciences",
      "year": 2026,
      "status": "Under review",
      "type": "article",
      "pages": null,
      "publisher": null,
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": null,
      "tags": ["computational pathology", "multimodal learning", "survival analysis"],
      "areas": ["ml"],
      "featured": false,
      "todo": []
    },
    {
      "id": "idjv-asr-tacl",
      "title": "Orthographic Convention, Pseudo-Labels and the Limits of System Combination in Code-Switched Indonesian–Javanese ASR",
      "authors": ["Sharoon Sharif", "N. O’Neill"],
      "author_note": null,
      "venue": "Transactions of the Association for Computational Linguistics (TACL)",
      "year": 2026,
      "status": "Under review",
      "type": "article",
      "pages": null,
      "publisher": null,
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": null,
      "tags": ["speech recognition", "low-resource languages", "code-switching"],
      "areas": ["ml"],
      "featured": false,
      "todo": []
    },
    {
      "id": "soma-sora-access",
      "title": "SOMA/SORA: A Symmetric Overloaded Instruction Set Architecture Family with FPGA Softcore Implementation and Pipelined Optimization",
      "authors": ["Sharoon Sharif", "Sita Kondamadugula", "Zhigang Xiao", "Patrick Jungwirth"],
      "author_note": null,
      "venue": "IEEE Access",
      "year": 2026,
      "status": "Under review",
      "type": "article",
      "pages": null,
      "publisher": "IEEE",
      "note": "Submitted Sept 2026",
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": null,
      "tags": ["computer architecture", "ISA", "FPGA", "softcore"],
      "areas": ["hardware"],
      "featured": false,
      "todo": []
    },
    {
      "id": "conv3x3-tcas2",
      "title": "A Bandwidth-Feasibility Model and Runtime-Programmable 3×3 Convolution Engine for Streaming Video on Zynq-7000 SoCs",
      "authors": ["Sharoon Sharif", "Sita Kondamadugula", "Zhigang Xiao"],
      "author_note": null,
      "venue": "IEEE Transactions on Circuits and Systems II: Express Briefs (special issue)",
      "year": 2026,
      "status": "Under review",
      "type": "article",
      "pages": null,
      "publisher": "IEEE",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": "https://github.com/SharoonSharif/conv3x3-engine-zynq" },
      "abstract": null,
      "summary": null,
      "tags": ["FPGA", "accelerator", "Zynq", "video", "performance modeling"],
      "areas": ["hardware"],
      "featured": false,
      "todo": []
    },
    {
      "id": "multi-drone-ral",
      "title": "Centralized vs. Decentralized Classical and Multi-Agent RL Policies for Multi-Drone Coordination: A Pre-Registered Study",
      "authors": ["Sharoon Sharif", "et al."],
      "author_note": "2nd author",
      "venue": "IEEE Robotics and Automation Letters (RA-L)",
      "year": null,
      "status": "In preparation",
      "type": "article",
      "pages": null,
      "publisher": "IEEE",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": "Compares a centralized planner, decentralized classical methods, and multi-agent RL (MAPPO/IPPO) for multi-drone coordination, with a decentralized safety filter robust to unannounced obstacle stops and validation in RotorPy. Pre-registered protocol with 17 pre-specified statistical comparisons.",
      "tags": ["multi-agent", "robotics", "reinforcement learning", "pre-registration"],
      "areas": ["robotics", "ml"],
      "featured": false,
      "todo": []
    },
    {
      "id": "fungi-acmse26",
      "title": "Hybrid Multi-Modal Learning for Extreme Long-Tail Fungi Classification",
      "authors": ["Sharoon Sharif", "Inikpi Egbunu", "Yujian Fu", "Zhigang Xiao"],
      "author_note": null,
      "venue": "Proceedings of the 2026 ACM Southeast Conference (ACMSE 2026)",
      "year": 2026,
      "status": "Published",
      "type": "inproceedings",
      "pages": "38–45",
      "publisher": "ACM",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": "10.1145/3746467.3801502", "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": null,
      "tags": ["multimodal learning", "long-tail classification"],
      "areas": ["ml"],
      "featured": false,
      "todo": []
    },
    {
      "id": "video-aiiot25",
      "title": "Hardware-Accelerated Video Processing System for Low-Powered Embedded Devices",
      "authors": ["Sharoon Sharif", "Sita Kondamadugula", "Zhigang Xiao", "Andrew Scott"],
      "author_note": null,
      "venue": "IEEE World AI IoT Congress (AIIoT)",
      "year": 2025,
      "status": "Published",
      "type": "inproceedings",
      "pages": "156–163",
      "publisher": "IEEE",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": "10.1109/AIIoT65859.2025.11105288", "bibtex": null, "scholar": null, "code": null },
      "abstract": "This study creates a hardware-accelerated video processing system for low-power embedded devices in two successive phases of implementation. The first establishes a real-time video pipeline using Zybo Z7020 FPGA with PCam camera to create the core system architecture with FPGA acceleration and HDMI output. In the second phase built on this first, the Sobel edge detection algorithms were integrated into the pipeline. A test of performance done in parallel, using the PYNQ board with USB camera, extends the system using a Python-based framework for simple hardware-software co-design and shows speed improvements and energy efficiency over software-only solutions, thus validating the approach for use in embedded vision applications.",
      "summary": null,
      "tags": ["FPGA", "video", "embedded vision", "HW/SW co-design"],
      "areas": ["hardware"],
      "featured": true,
      "todo": []
    },
    {
      "id": "image-aiiot25",
      "title": "Hardware-Software Co-Designed Embedded System for Efficient Image Processing",
      "authors": ["Sharoon Sharif", "Sita Kondamadugula", "Zhigang Xiao", "Andrew Scott"],
      "author_note": null,
      "venue": "IEEE World AI IoT Congress (AIIoT)",
      "year": 2025,
      "status": "Published",
      "type": "inproceedings",
      "pages": "950–954",
      "publisher": "IEEE",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": "10.1109/AIIoT65859.2025.11105252", "bibtex": null, "scholar": null, "code": null },
      "abstract": "This research work is based on developing a real-time image processing system to detect edges of the image using the Sobel algorithm on Zybo Z7020 FPGA, applying the hardware-software co-design methodology. This system is able to process images in real-time on FPGA-based hardware which accelerates the overall process when coupled with the dedicated software application, which controls these hardware processes, significantly reduces the latency and power consumption thus making the system well suited to be used in embedded systems. Resultantly, the image processing system i.e. Sobel Edge Detection is designed in Verilog for FPGA hardware, whereas software handles the system control, including initialization and display output. The design, being modular, is scalable and easy to apply; the system works in real-time with low latency and low power consumption.",
      "summary": null,
      "tags": ["FPGA", "image processing", "HW/SW co-design"],
      "areas": ["hardware"],
      "featured": false,
      "todo": []
    },
    {
      "id": "mips-ccwc25",
      "title": "Design and Implementation of 32-bit MIPS-based Softcore Processor with Enhanced Instruction Set on FPGA",
      "authors": ["Sharoon Sharif", "Sita Kondamadugula", "Patrick Jungwirth", "Zhigang Xiao", "Andrew Scott"],
      "author_note": null,
      "venue": "IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC)",
      "year": 2025,
      "status": "Published",
      "type": "inproceedings",
      "pages": "896–900",
      "publisher": "IEEE",
      "note": null,
      "award": "Best Presentation Award",
      "links": { "pdf": null, "doi": "10.1109/CCWC62904.2025.10903946", "bibtex": null, "scholar": null, "code": null },
      "abstract": "In this paper, the 32-bit MIPS HDL processor has been devised to serve the purpose of running Symmetric and Overloaded Instruction Set (SOMA) on an FPGA. The SOMA architecture is unique in its overloaded and branching instructions. With a Verilog processor developed based on the SOMA design, the feasibility of SOMA on hardware is proven. This design has evident optimizing resource utilization. The findings make significant contributions to the improvement of the methodologies used in designing processors and that FPGAs are less expensive and practical Hardware platforms to test the designs. A 32-bit processor is implemented in HDL with 20 instructions and can handle memory of 32 registers. Design is tested and implemented on Xilinx DDR 4 FPGA board. Synthesis results were evident that the SOMA register-integer class and Branch class are practical.",
      "summary": null,
      "tags": ["computer architecture", "ISA", "FPGA", "softcore"],
      "areas": ["hardware"],
      "featured": false,
      "todo": []
    },
    {
      "id": "mips-ictis24",
      "title": "Optimization and Implementation of a 32-bit MIPS-based Softcore Processor to run Statistical Algorithms on FPGA",
      "authors": ["Sharoon Sharif", "Meek Simbule", "Tiger Cabbil", "Sita Kondamadugula", "Zhigang Xiao", "Andrew Scott"],
      "author_note": null,
      "venue": "ICT for Intelligent Systems (ICTIS 2024), Smart Innovation, Systems and Technologies",
      "year": 2024,
      "status": "Published",
      "type": "inproceedings",
      "pages": "365–374",
      "publisher": "Springer",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": "10.1007/978-981-97-5810-4_32", "bibtex": null, "scholar": null, "code": null },
      "abstract": "The study focuses on the design optimization of the 32-bit MIPS-based processor to make it eligible to execute the statistical algorithms with pipelined architecture. Symmetric Overloaded Minimal Instruction Set Architecture (SOMA) (Jungwirth et al. in SoutheastCon 2023, Orlando, FL, USA, pp. 53–59, 2023 [1]) instruction set architecture and 4-stage pipeline is incorporated in the design to make the processor efficient for the statistical algorithms’ execution. For this study, a processor is designed in Verilog HDL, tested on the NEXYS DDR 4 FPGA board using Xilinx Vivado 2020.2. The comparison between 32-bit single-cycle MIPS-based processor and 32-bit SOMA ISA and 4-stage pipeline processor showed significant improvement in reducing the number of clock cycles and use of the number of registers/memory. Therefore, the study also proves the SOMA ISA with 4-stage pipelined version outperforms FPGA with MIPS-based architecture in terms of time consumption and memory usage. Study also suggests that FPGAs are less costly hardware testing platforms for new designs in the field of computer architecture, digital design, and microprocessors.",
      "summary": null,
      "tags": ["computer architecture", "pipelining", "FPGA", "softcore"],
      "areas": ["hardware"],
      "featured": false,
      "todo": []
    },
    {
      "id": "ms-thesis",
      "title": "AI-Guided Image/Video Processing Techniques Implemented on FPGA Hardware",
      "authors": ["Sharoon Sharif"],
      "author_note": "Advisor: Dr. Zhigang Xiao",
      "venue": "MS Thesis, Alabama A&M University",
      "year": 2025,
      "status": null,
      "type": "thesis",
      "pages": null,
      "publisher": null,
      "school": "Alabama A&M University",
      "note": null,
      "award": null,
      "links": { "pdf": null, "doi": null, "bibtex": null, "scholar": null, "code": null },
      "abstract": null,
      "summary": null,
      "tags": ["FPGA", "computer vision", "HW/SW co-design"],
      "areas": ["hardware", "ml"],
      "featured": false,
      "todo": []
    }
  ]
}