Die mapHover or tap a block to open a research area01
About
Bio
I build hardware and software that let machine learning run efficiently on constrained devices. My work spans the stack: I've designed and optimized processors from the instruction set up, built FPGA accelerators for real-time video, and developed ML models for computational pathology, long-tail recognition and low-resource speech.
I hold an MS in Electrical Engineering from Alabama A&M University (4.0 GPA), where my thesis focused on AI-guided image and video processing on FPGA hardware.
Now
AI Integration Specialist, building speech and language AI for low-resource languages: production TTS and ASR, and agentic LLM systems.
Stack
ISA
RTL
FPGA
ML models
Deployed AI
Interests
FPGA & reconfigurable computing
Domain-specific accelerators
HW/SW co-design for edge ML
Computer architecture & ISA design
Multimodal & long-tail learning
Low-resource speech
Off the clock
Away from work I'm usually travelling, cooking, or reading classic literature.
02
Research
Six blocks on one die. Each card matches a block in the map above.
BLK 01 · CPU · ISA
Softcore processors & ISA design
FPGA softcores for the SOMA and SORA instruction sets introduced by Jungwirth et al. (SoutheastCon 2023, 2024), taken from a single-cycle design to a four-stage pipeline, and 32-bit MIPS-based softcores with extended instruction sets.
A runtime-programmable AXI4-Stream 3×3 convolution engine for the Zynq-7020 with an analytical DDR bandwidth-feasibility model for streaming video, and a real-time PCam → Sobel → HDMI pipeline compared against Python on PYNQ. Public RTL, self-checking testbenches and post-route reports.
PathQ-Former: an audit of whether histology–transcriptomics survival models actually use the transcriptome, and a one-checkpoint recipe that keeps working when a modality is missing. Five TCGA cohorts, multiple-comparison correction, and explicit reporting of where it does not beat baselines.
Production TTS/ASR pipelines for low-resource languages, and a study of how orthographic convention, pseudo-labels and system combination shape code-switched Indonesian–Javanese ASR.
A pre-registered comparison of centralized planning, decentralized classical methods and multi-agent RL (MAPPO/IPPO) for multi-drone coordination, with a decentralized safety filter (2nd author).
IEEE CCWC 2025Presenting the MIPS/SOMA softcore paper, which won the Best Presentation Award.IEEE AIIoT 2025Presenting hardware–software co-design work for FPGA image and video processing.Alabama A&M · 2024Receiving the Outstanding Graduate Student Award.
Production TTS/ASR pipelines for low-resource languages.
Agentic platforms, Claude API/MCP integrations, and workflow automation.
Graduate Research Assistant
Aug 2023 – May 2025
Alabama A&M University
Machine learning and hardware systems: long-tail multimodal classification (Dr. Yujian Fu), AI-guided image/video processing on FPGA (Dr. Zhigang Xiao), and softcore processor and ISA design (Drs. Xiao, Jungwirth, Scott).
Graduate Teaching Assistant
Aug 2023 – May 2025
Alabama A&M University
Computer Architecture, Microprocessors, Linear Circuit Analysis, and Analog Circuits labs.
Program Coordinator
Nov 2019 – Aug 2023
National Commission for Justice and Peace, Lahore, Pakistan
Earlier Communications Coordinator and Program Assistant. Human-rights programs, monitoring and evaluation, survey and focus-group research, and policy reports.
Research Intern
Jan – Dec 2017
Micro-Nano Lab, Information Technology University of the Punjab